The HiLeS2 Framework was developed to aid the Embedded System Designers during the design process. The HiLeS2 Framework purpose is to serve as a platform to create Embedded System Product Lines. It incorporates both tools developed by the group and open source tools to provide an Integrated Development Environment (IDE) suitable for system specification, product line construction and virtual prototype generation. The HiLeS2 Framework serves as a tool for:
- System-level design in SysML
- Visualization and validation of the system-level model in SysML (Papyrus Editor)
- Automatic Virtual Prototype (VP) generation in Hardware Description Language.
- Visualization of intermediate models
- Specialized "per Product Line" IDE construction: definition of base assets and configuration options for a specific family of products.
- Access to Fiesta set of tools for Product Line definition
- Interface to TINA: formal Petri Net verification tool for HiLeS model validation
The Specialized IDE in turn serves as a tool for:
- Product Configuration
- Intellectual Properties (IP) search and retrieval
- Refined VP generation
- Duration Constraint Validation (VP simulation vs. system requirements)
The HiLeS Framework supports the design process presented in Figure 1. Initially the Domain Engineer constructs the system level model of the base platform using SysML. Then using the Framework tools generates the HiLeS model of the system's platform. The system is then validated with TINA. If the Validation is ok, the VP in VHDL-AMS and Verilog-AMS are constructed for platform verification through simulation. Then the domain engineer defines the variability of the platform and constructs the specialized IDE. Then the Product Engineer can configure specific products and generate VP of them. IN the case of VHDL-AMS prototypes, the product engineer can use Tucan to validate duration constraints.
